It struck me that a project like this is a perfect excuse to get some experience with FPGAs, so I thought I'd start out by sketching out a high-level design that I can use for component selection and so on. It seems like a rather straightforward task, although as always the devil is in the details -- and everything looks easy until the reality sets in!
My basic requirements are:
- 2 channels of output
- 200 MSPS output sample rate
- +-/- 10 volt output range; reasonable fidelity down to 10-ish millivolts peak to peak
- Enough output current to drive a 50-ohm transmission line (plus a bit more). 250 mA is probably enough, 500 would be nice
- Basic set of signal types, including pulse trains, amplitude modulation, etc. Details to be worked out later
Here is a block diagram showing all the parts (just one output channel shown for simplicity). Below the diagram, each part is briefly explained:
- Power: Regulators to provide all the power rails needed, from a +12v input
- LCD for nice UI
- Touchscreen to simplify setting complex parameters
- Buttons and knobs for functions that operate better from hard controls
- External communication (USB probably)
- Accurate low-jitter clock generator to synchronize the MCU/FPGA/DAC and drive conversion
- Microcontroller for UI, communication, and FPGA control
- FPGA: almost certainly I will use a Spartan 6, which is pretty powerful, inexpensive, and solder-friendly
- DAC: I picked up a couple cheap DAC5672 on ebay: dual 14-bit 275 MSPS in easy TQFP-48 package
- Current to voltage conversion
- Filter to exclude high frequencies (which come from "steps" in the conversion). Still want square waves to be square, though, so it's a tradeoff.
- Amplification to output voltage range. Ideally this would be externally programmable (shown here with an auxiliary DAC), from -20dB to +20dB. The details need to be worked out.
- Gain control for the amplifier
- AC coupling to remove any offset artifacts
- High-current output buffer. Also moves the signal to its target common-mode voltage.
- Common-mode output voltage control for the output buffer
- Signal buffer for feedback measurement pathway
- Fixed attenuator to move the signal down to a range the ADC can handle
- ADC for signal measurement during self-calibration
- Solid-state relay to shut off the output (under user control and also during self-calibration)
- Impedance control for output transmission line
- Output jack (BNC)
I have a little Spartan 6 development board, so the next step will be the agonizing component-selection process, after which I will construct a prototype of the output stage (all the stuff shown in yellow and blue).
Also I will work more on specifying features so I can think more carefully about how to implement it in the FPGA. Since I haven't ever used an FPGA in a project so far, it will be something of a learnign curve... but that is 68.2% of the fun!
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